The brand new implication of actual HW limits towards programming model try this one you should never index dynamically across the technology data: a register file can basically not be detailed dynamically. The reason being the fresh register number is restricted and one either should unroll clearly to acquire repaired register amounts or wade owing to thoughts. This is exactly a constraint familiar so you’re able to CUDA programmers: when saying an exclusive drift a beneficial ; and you can subsequently indexing with a dynamic worth causes therefore-entitled local memories usage (we.elizabeth. roundtripping in order to memory).
Implication toward codegen ¶
It raises the results towards static versus active indexing discussed in the past: extractelement , insertelement and you can shufflevector to the letter-D vectors during the MLIR just support fixed indices. Dynamic indices are only served on the very small step 1-D vector yet not this new external (n-1)-D . With other circumstances, specific weight / stores are needed.
- Loops doing vector beliefs try indirect handling out of vector opinions, they must operate on direct weight / shop operations more letter-D vector sizes.
- Just after a keen letter-D vector method of are stacked with the a keen SSA worth (that or might not live in n registers, with otherwise instead spilling, when eventually reduced), it could be unrolled in order to less k-D vector brands and operations that correspond to the HW. So it level of MLIR codegen is related to check in allotment and you will spilling you to exists much later on throughout the LLVM tube.
- HW will get help >1-D vectors with intrinsics to own secondary addressing in these vectors. These could feel targeted through direct vector_throw procedures off MLIR k-D vector designs and operations in order to LLVM 1-D vectors + intrinsics.
Alternatively, i argue that directly minimizing in order to a linearized abstraction covers aside new codegen complexities pertaining to memories accesses by giving a bogus impact of phenomenal active indexing round the reports. Rather i will make people very direct when you look at the MLIR and ensure it is codegen to explore tradeoffs. Additional HW requires some other tradeoffs on the brands doing work in procedures 1., dos. and you will step three.
Decisions made from the MLIR top are certain to get implications on a great much later on phase in the LLVM (shortly after sign in allocation). We do not consider to reveal issues connected with acting from check in allotment and you will spilling so you’re able to MLIR clearly. Rather, each target usually present some “good” address operations and you may letter-D vector models, from the will set you back you to PatterRewriters at MLIR level would-be able to target. Such as for instance will set you back at the MLIR height could well be abstract and you may made use of to own positions, maybe not getting direct results modeling. Later including will cost you might be read.
Implication into Lowering so you can Accelerators ¶
To target accelerators that support higher dimensional vectors natively, we can start from either 1-D or n-D vectors in MLIR and use vector.cast to flatten the most minor dimensions to 1-D vector
It is the role of an Accelerator-specific vector dialect (see codegen flow in the figure above) to lower the promo kódy blackplanet vector.cast . Accelerator -> LLVM lowering would then consist of a bunch of Accelerator -> Accelerator rewrites to perform the casts composed with Accelerator -> LLVM conversions + intrinsics that operate on 1-D vector
Some of those rewrites may need extra handling, especially if a reduction is involved. For example, vector.cast %0: vector
However vector.cast %0: vector